Checked 24 October 2026 against arXiv HTML 2511.05506v1 and two imec articles. No bond was run here.

The pad does not land where you drew it

Hybrid bonding joins two finished faces with copper pads in a dielectric and no solder bump between them. The pads move. A route that ignores the move will bless a link the bond cannot make.

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What this reading changed

An earlier draft of this note said the allowance δ had no printed form, and that a die score must not raise one pad’s odds to the pad count. Both lines were too blunt. Equation (6) of YAP+ does print δ. For overlay, equation (7) scores the die by the worst critical or redundant pad, which is a minimum, not a product. Copper-recess yield is a different formula, and that one does raise the critical-pad term to the count of critical pads. Resistivity, copper-expansion, and die-to-wafer yield figures from other papers are off this page until those PDFs are opened.

The field

Chen and Gupta split misalignment into a systematic field and a random residual. Magnification tracks bow. They fit E = k_mag · B. At a pad designed at (x, y), their equation (3) is:

Δx = T_x − α y + E x
Δy = T_y + α x + E y
s  = √(Δx² + Δy²)

T_x and T_y are translations. α is the small rotation. E is the magnification. s is the offset at that pad. The same pair is one matrix plus a shift. This inverse is the algebra of their equations. They do not print it.

[ x' ]   [ 1+E   −α ] [ x ]   [ T_x ]
[ y' ] = [  α   1+E ] [ y ] + [ T_y ]

A⁻¹ = 1/((1+E)² + α²) · [ 1+E    α ]
                           [  −α   1+E ]

If the bonder applies A and t, the pads are printed at A⁻¹(p − t) so the bond lands on the designed point. Imec calls the same move a pre-bond lithography correction. On their page, that correction reached a 300 nm pitch with overlay under 25 nm on 95% of the dies, on current bonders. A low-order inverse does not remove a bonding wave that is uneven. Imec’s simulations say the wave does not propagate uniformly, and that uneven wave bends the wafer.

One pad, then the worst pad

After the systematic field is removed, the residual is modeled as normal, mean zero, width σ₁. One pad survives when the residual stays inside ±δ. Their equation (1):

POS = 1 / (σ₁ √(2π)) · ∫ from −δ to δ of exp(−u² / (2 σ₁²)) du

δ is the smaller of two limits. The first comes from still having enough copper overlap. The second comes from still having enough dielectric gap to the neighbor. Their equation (6), as printed:

δ = min{ (θ1 r1² + θ2 r2² − k_ca π r1²) / (r1 sin θ1) ,
         (1 − k_cd) p − d1/2 + (k_cd − 1/2) d2 }

θ1 and θ2 are the sector angles of the partial overlap. They still depend on the offset, so the first branch is not a number you can drop in before the geometry is known. The overlap area itself, their equation (5), has three cases. The contained case assumes the bottom radius is at least the top radius.

• s < r2 − r1: S = π r1²
• r2 − r1 ≤ s ≤ r1 + r2: S = θ1 r1² + θ2 r2² − s r1 sin θ1
• s > r1 + r2: S = 0, and the link is open

A pad is alive when the overlap is still above k_ca times the top pad area, and the remaining neighbor gap is still above k_cd times the designed gap. The designed gap is p − d2.

The die’s overlay score is not that single-pad integral raised to the pad count. Equation (7) takes the minimum over the critical and redundant pads, and it shifts each integral by that pad’s own systematic error s_i. Dummy pads are left out. Power and ground pads with many widely spread copies are left out too. The paper’s reason is that a die is very unlikely to die only because every one of those copies failed together. Wafer overlay yield, equation (8), is the average of those die scores.

Copper recess is the other formula. There, the critical-pad survival is raised to the number of critical pads, and each redundant group survives if one of its replicas survives. Using the overlay rule on the recess, or the recess rule on the overlay, scores the wrong failure.

Which pads carry a net

YAP+ keeps the roles split. The sentences below are theirs.

Particles are a third model. A void can be much larger than the pitch, and YAP+ estimates the pads it covers by dilating the defect over the real layout. That dilation is not the overlay integral.

They also record a recommendation, cited to another paper: keep total misalignment inside 50% of the bottom pad diameter. That is a cited target, not a result of this reading.

What imec’s own pages say

These sentences were on the imec pages opened for this check.

• The classical flow is damascene cavities, barrier and copper fill, polish with a few nanometers of copper recess, contact at the center, a bonding wave to the edge, then anneal. SiO2 is the dielectric they call predominant in that classical description. For the 400 nm pitch they report SiCN as stronger and more scalable than SiO2.
• At IEDM 2023 they showed 400 nm pitch wafer-to-wafer bonds on 300 mm wafers, with overlay below 150 nm. On that same pitch they concluded overlay needs to be under 100 nm for enough yield in high-volume manufacturing.
• Commercial image-sensor and 3D-NAND stacking, as they describe it, sits near a 1 µm pitch and about a million interconnects per square millimeter.
• Their rule of thumb is overlay of about one quarter of the pitch: 50 nm of overlay for a 200 nm pitch. The roadmap they name is 200 nm.
• At VLSI 2025 they call 250 nm pitch feasible on a hexagonal grid with unequal pads. Full-wafer yield at the overlay that pitch needs, they say, waits on a newer bonder.
• The same VLSI report includes backside through-dielectric vias with a 20 nm bottom diameter on a 120 nm pitch.

The overlay matrix is the bonder’s translation, rotation, and magnification. It is a separate geometry from the authorization distance used elsewhere on this site.

Sources opened for this page

• Zhichao Chen and Puneet Gupta, YAP+, arXiv:2511.05506v1, submitted 20 October 2025. Equations (1) through (8) were read in the HTML. The v1 comment still says the paper is under review at IEEE TCAD. IEEE Xplore lists a published version, vol. 45, no. 10, pp. 4814–4827, 23 January 2026, DOI 10.1109/TCAD.2026.3657674. The journal PDF was not the file read for the equations. Author code, as linked by the paper: nanocad-lab/YAP. That repository was not run here.
• imec, wafer-to-wafer hybrid bonding at 400 nm pitch.
• imec, front- and backside wafer connectivity, including the 300 nm pre-bond result, the 250 nm pitch, and the 20 nm backside vias.